1. Field of the Invention
The present disclosure generally relates to the fabrication of integrated circuits, and, more particularly, to methods of testing an integrity of a material layer provided in a semiconductor structure.
2. Description of the Related Art
Integrated circuits comprise a large number of individual circuit elements, e.g., transistors, capacitors and resistors, formed on and in a substrate. These elements are connected internally by means of electrically conductive lines to form complex circuits, such as memory devices, logic devices and microprocessors. To accommodate all the electrically conductive lines required to connect the circuit elements in modern integrated circuits, the electrically conductive lines are arranged in a plurality of levels stacked on top of each other. To connect electrically conductive lines provided in different levels, contact vias are formed in dielectric layers separating the levels from each other. These vias are then filled with an electrically conductive material.
A method of forming an electrically conductive line according to the state of the art will now be described with reference to FIGS. 1a and 1b. FIG. 1a shows a schematic cross-sectional view of a semiconductor structure 100 in a first stage of the method of forming an electrically conductive line according to the state of the art. A semiconductor substrate 101 is provided. The semiconductor substrate 101 may comprise a plurality of circuit elements and, optionally, electrically conductive lines in lower interconnect levels. The semiconductor substrate 101 further comprises a first dielectric layer 102 formed thereon. A trench 107 is formed in the dielectric layer 102. A trench fill 111 comprising an electrically conductive material, e.g., a metal, such as copper, is provided in the trench 107. The trench fill 111 forms an electrically conductive line. A diffusion barrier layer 110 separates the trench fill 111 from the first dielectric layer 102. Thus, a diffusion of the material of the trench fill 111 into the first dielectric layer 102 can be prevented and adhesion between the trench fill 111 and the dielectric material of the first dielectric layer 102 can be improved. The semiconductor substrate 101 can be formed by means of methods known to persons skilled in the art comprising advanced techniques of deposition, oxidation, ion implantation, etching and photolithography.
An etch stop layer 103 is formed over the semiconductor substrate 101. In addition to the surface of the first dielectric layer 102, the etch stop layer 103 covers an exposed top surface of the trench fill 111. On the etch stop layer 103, a second dielectric layer 104 is formed. The second dielectric layer 104 may comprise the same material as the first dielectric layer 102. The etch stop layer 103 and the second dielectric layer 104 may be formed by means of methods known to persons skilled in the art, such as chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD) and spin coating.
A trench 109 and a contact via 108 are formed in the second dielectric layer 104. This can be done by photolithographically forming a mask (not shown) which exposes a portion of the surface of the second dielectric layer 104 at the location where the contact via 108 is to be formed. Then, an etching process is performed. To this end, the semiconductor structure 100 is exposed to an etchant adapted to selectively remove the material of the second dielectric layer 104, leaving the etch stop layer 103 essentially intact. Thus, the etching process stops as soon as the etch front reaches the etch stop layer 103.
The etching process may be anisotropic. In anisotropic etching, a rate at which material is removed from the etched surface depends on the orientation of the surface. In an anisotropic etching process, the etch rate of substantially horizontal portions of the etched surface being substantially parallel to the surface of the semiconductor substrate 101 is significantly greater than the etch rate of inclined portions of the etched surface. Thus, substantially no material below the mask is removed and the via 108 obtains substantially vertical sidewalls. Thereafter, the mask is removed, which can be done by means of a resist strip process known to persons skilled in the art, and the trench 109 is formed. Similar to the formation of the contact via 108, the trench 109 can be formed by photolithographically forming a mask on the semiconductor structure 100 and performing an anisotropic etching process.
Subsequently, a portion of the etch stop layer 103 exposed at the bottom of the contact via 108 is removed. The exposed portion of the etch stop layer 103 may be removed by means of an etching process adapted to selectively remove the material of the etch stop layer 103, leaving the materials of the second dielectric layer 104 and the trench fill 111 substantially intact.
A diffusion barrier layer 105 is deposited on the semiconductor structure 100. In particular, the diffusion barrier layer 105 covers the sidewalls and the bottom of the trench 109 and the contact via 108. This can be done by means of known methods such as CVD, PECVD and/or sputter deposition. Then, a layer 106 of an electrically conductive material, e.g., copper, is formed on the diffusion barrier layer 105. To this end, methods of electroplating known to persons skilled in the art may be employed.
The diffusion barrier layer 105 may comprise materials such as titanium nitride, tantalum and/or tantalum nitride which may prevent a diffusion of the electrically conductive material of the layer 206 into the second dielectric layer 104 and other portions of the semiconductor structure 100. In particular, in methods of forming an electrically conductive line according to the state of the art wherein the electrically conductive material comprises copper, the diffusion barrier layer 105 may prevent a diffusion of copper into circuit elements such as field effect transistors formed in the semiconductor structure 100. This may help avoid adverse effects of the presence of copper on the functionality of the field effect transistors.
FIG. 1b shows a schematic cross-sectional view of the semiconductor structure 100 in a later stage of the method of forming an electrically conductive line according to the state of the art. The surface of the semiconductor structure 100 is planarized, for example, by means of a known chemical mechanical polishing (CMP) process. In the planarization, portions of the diffusion barrier layer 105 and the layer 106 outside the trench 109 and the contact via 108 are removed and a planar surface of the semiconductor structure 100 is obtained. Residues of the layer 106 in the trench 109 form an electrically conductive line. Residues of the layer 106 in the contact via 108 provide an electrical contact between the electrically conductive lines in the trench 109 and the trench 107.
A problem of the above-described method of forming an electrically conductive line according to the state of the art is that the diffusion barrier layer 105 may comprise one or more pores 112. During the formation of the layer 106 of electrically conductive material, the presence of the pore 112 may induce an insufficient filling of the contact via 108 with the electrically conductive material such that a void 113 is created in the layer 106.
If the semiconductor structure 100 is operated after the completion of the manufacturing process, the void 113 may increase the electrical resistance of the electrically conductive line formed in the contact via 108. Additionally, the presence of the void 113 may increase the likelihood of electromigration and/or stress migration occurring.
As persons skilled in the art know, the term “electromigration” denotes a current-induced transport of atoms in conductors. Electrons moving in an electrical field exchange momentum with the atoms. At high current densities, the momentum imparted to the atoms forms a net force which is high enough to propel atoms away from their sites in the crystal lattice. Thus, the atoms pile up in the direction of electron flow. The likelihood of electromigration is dependent, inter alia, on temperature, wherein moderately high temperatures increase the likelihood of electromigration occurring.
Moreover, undesirable material transport in semiconductor structures may be caused by mechanical stress which can be created, for example, due to different thermal expansion coefficients of materials present in the semiconductor structure 100. Such stress may relax via a diffusion of atoms in the electrically conductive line. The diffusion of atoms entails a transport of material. This phenomenon is denoted as “stress migration.”
In the void 113, there is a surface of the material of the layer 106. At the surface, there is a greater likelihood of electromigration occurring than in other portions of the electrically conductive line in the contact via 108 and/or in the trench, since the material at the surface of the layer 106 is not confined by the barrier layer 108 and/or other elements of the semiconductor structure 100. In the course of time, electromigration and/or stress migration may negatively affect or even destroy the electrically conductive line formed in the contact via 108.
Therefore, it is desirable to develop methods of forming a diffusion barrier layer which eliminates or at least reduces the likelihood of the formation of pores. Methods which allow testing the integrity of a diffusion barrier layer are helpful for this purpose.
In the state of the art, it has been proposed to investigate a diffusion barrier layer by means of transmission electron microscopy. For this purpose, a sample comprising a thin section of a semiconductor structure similar to the semiconductor structure 100 described above is employed. A problem of this technique, however, is that the preparation of samples adapted for transmission electron microscopy, as well as transmission electron microscopy itself, are difficult to perform and are time-consuming. This may restrict the number of contact vias which can be investigated in an economically feasible manner, and may impose difficulties in implementing routine or in-line processes for testing the integrity of the diffusion barrier layer.
The present disclosure is directed to various methods that may avoid, or at least reduce, the effects of one or more of the problems identified above.